[libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog

[Luke Kenneth Casson Leighton]

On Wednesday, May 13, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:

> On Tue, May 12, 2020, 08:04 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > the next level up from that would be to say, "ok now do a 128-bit
> > adder", and they will struggle to create efficient-looking code in
> > VHDL, because they will end up cut/pasting 128 full-adders into the
> > file.  the point of *that* exercise being to point out to them that
> > VHDL (and verilog) are *not* adequate modern languages (they never
> > were), and that nmigen you can use a *python for-loop* to create - and
> > link up - the 128 full-adders.
> >
>
> That may not be an adequate demonstration, since a 128-bit ripple adder can
> be implemented in a few lines using the following pseudo-Verilog:
>
> module full_adder(a, b, c_in, c_out, o);
>     wire [127:0] a, b, c_in, c_out, o;
>     assign o = a ^ b ^ c_in;
>     assign c_out = (a & b) | (a & c_in) | (b & c_in);
> endmodule


that's the simple version (and a cool one), i was thinking in terms of a
suite of single-bit full adders that then need to be manually linked up.

in verilog or vhdl this is a total pain.

in nmigen it is just a for loop with setattr(m.submodules, "fulladd%d" % i,
fainstance)

the very simplicity of doing a full adder is why it would work as a rapid
demonstration of using python for HDL.

if the exercise were more complex the design of the submodule would
distract from the point.

l.



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