[libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog

[Jacob Lifshay]

On Tue, May 12, 2020, 08:04 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> the next level up from that would be to say, "ok now do a 128-bit
> adder", and they will struggle to create efficient-looking code in
> VHDL, because they will end up cut/pasting 128 full-adders into the
> file.  the point of *that* exercise being to point out to them that
> VHDL (and verilog) are *not* adequate modern languages (they never
> were), and that nmigen you can use a *python for-loop* to create - and
> link up - the 128 full-adders.
>

That may not be an adequate demonstration, since a 128-bit ripple adder can
be implemented in a few lines using the following pseudo-Verilog:

module full_adder(a, b, c_in, c_out, o);
    wire [127:0] a, b, c_in, c_out, o;
    assign o = a ^ b ^ c_in;
    assign c_out = (a & b) | (a & c_in) | (b & c_in);
endmodule

module adder(a, b, c_in, c_out, o);
    wire [127:0] a, b, o, c;
    wire c_in, c_out;
    full_adder fa(
        .a: a,
        .b: b,
        .o: o,
        .c_in: {c[126:0], c_in},
        .c_out: c,
    );
    assign c_out = c[127];
endmodule

Jacob