[libre-riscv-dev] daily kan-ban update 12may2020

[Luke Kenneth Casson Leighton]

On Tue, May 12, 2020 at 3:43 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:
>
> I’m currently attending Create-X startup school at Launch 2020 - for Systèmes Libres.
>
> I also got hired by Georgia Tech to help re-write the computer architecture class.
> The reason I mention this is that classes like these are very formative for students -
> and perhaps one of these students might contribute to Libre-SOC in the future.

that's a really good idea.

> With that in mind, I tried to incorporate concepts such as git, using nMigen, Cocotb, etc…

honestly, if they're learning verilog and VHDL as the primary HDL,
it's like teaching 1980s programming.  i mean, it's _good_ that they
learn those - but move very very swiftly on.

something that might be really good to include as a teaching aid is
that online javascript logic simulation thing.  just to get them the
absolute basics of logic gates.

even something as basic as "design a 4-bit adder at the gate level....
now redo it in VHDL, and now redo it in nmigen" would be a really
instructive and eye-opening exercise - particularly if first specified
as "for a first version you're allowed in VHDL and nmigen to do it
using the "add" operator, but the second version you are not: it must
be done with half and full adders, as modules".

that would hammer home to them the significance of even using
something as quotes basic quotes as the "add" operator in nmigen and
VHDL.

the next level up from that would be to say, "ok now do a 128-bit
adder", and they will struggle to create efficient-looking code in
VHDL, because they will end up cut/pasting 128 full-adders into the
file.  the point of *that* exercise being to point out to them that
VHDL (and verilog) are *not* adequate modern languages (they never
were), and that nmigen you can use a *python for-loop* to create - and
link up - the 128 full-adders.

end-result: about 50 lines of python code instead of 300+ lines of
heavily-duplicated VHDL.

l.