[libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
programmerjake at gmail.com
Wed May 13 20:02:41 BST 2020
On Wed, May 13, 2020, 11:52 Michael Nolan <mtnolan2640 at gmail.com> wrote:
> On 5/13/20 2:18 PM, Luke Kenneth Casson Leighton wrote:
> > that's the simple version (and a cool one), i was thinking in terms of a
> > suite of single-bit full adders that then need to be manually linked up.
> > in verilog or vhdl this is a total pain.
> I agree it's easier to do in nmigen, but both verilog and vhdl support
> generate statements for doing just that.
Maybe a better (though maybe not realistic) example is trying to xor all
input bits where the bits' indexes are prime numbers, that would be
relatively easy in nmigen but quite hard in VHDL or Verilog.
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