[libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed May 13 20:54:06 BST 2020

On Wednesday, May 13, 2020, Michael Nolan <mtnolan2640 at gmail.com> wrote:

> On 5/13/20 2:18 PM, Luke Kenneth Casson Leighton wrote:
>> that's the simple version (and a cool one), i was thinking in terms of a
>> suite of single-bit full adders that then need to be manually linked up.
>> in verilog or vhdl this is a total pain.
>> I agree it's easier to do in nmigen, but both verilog and vhdl support
> generate statements for doing just that.

oh! nice! i kinda learned them both by osmosis :)

so it would be a side by side comparison of how to do submodules.

i wonder where it gets really difficult (primes is a nice example, jacob).

i know.  something where you pass in different Record layouts in nmigen.
VHDL you would have to do macro substitution of the record type, and only
mentor graphics sv supports records as arguments to modules.

then the next horrible thing to do would be a multiple inheritance python
module, or, like in the FP code surrounding ctx and pspec, use dynamic
classes that override __new__.

first time i did something like that and actually had to ask on
stackoverflow :)

even just passing in the class (ctx kls) would cause a seasoned verilog HDL
engineer to blow a fuse :)


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