[libre-riscv-dev] [Bug 316] bperm TODO

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=316

--- Comment #3 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Yehowshua from comment #2)
> Change line 13 to 
> ``m.d.comb += self.perm.eq(0)``
> 
> You don't need to use ``Cat`` and or ``Repo``. nMigen knows how to 0 pad and
> sign extend.
> 
> Now you'll get another issue - namely, that rs isn't define...
> 
> What is Bpermd supposed to do?
> You should put a Python class comment as shown below to help readers
> understand.
> 
> ```
> class Bpermd(Elaboratable):
> """This class does X,Y, and Z"""
>     def __init__(self, width):
>         self.perm = Signal(width)
> ```

Thanks so much for your help Yehowshua! I've done as you reccomended and added
a doc string, as well as changing line 13, and referring to ra and rb with the
self prefix. Now I am getting a different error, perhaps you could advise me as
to how to proceed?
 1 bperm.py                                                                    
                                                      X 
 from nmigen import Elaboratable, Signal, Module, Repl, Cat
 from nmigen.cli import main

 class Bpermd(Elaboratable):
     """This class does a Bit Permute on a Doubleword

        X-form bpermd RA,RS,RB]
 [snip]
     """

     def __init__(self, width):
         self.perm = Signal(width)
         self.rs   = Signal(width)
         self.ra   = Signal(width)
         self.rb   = Signal(width)

     def elaborate(self, platform):
         m = Module()
         m.d.comb += self.perm.eq(0)
         index = Signal(8)
         for i in range(0, 7 + 1):
             index = self.rs[8 * i:8 * i + 7 + 1]
             with m.If(index < 64):
                 m.d.comb += self.perm[i].eq(self.rb[index])
             with m.Else():
                 m.d.comb += self.perm[i].eq(0)
         m.d.comb += self.ra.eq(Cat(Cat(0,Repl(56)), self.perm[0:8]))
         return m

 if __name__ == "__main__":
     bperm = Bpermd(width=64)
     main(bperm,ports=[bperm.perm, bperm.rs, bperm.ra, bperm.rb])
```


Traceback (most recent call last):
  File "bperm.py", line 50, in <module>
    main(bperm,ports=[bperm.perm, bperm.rs, bperm.ra, bperm.rb])
  File "/home/colepoirier/src/nmigen/nmigen/cli.py", line 74, in main
    main_runner(parser, parser.parse_args(), *args, **kwargs)
  File "/home/colepoirier/src/nmigen/nmigen/cli.py", line 65, in main_runner
    fragment = Fragment.get(design, platform)
  File "/home/colepoirier/src/nmigen/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
  File "bperm.py", line 42, in elaborate
    m.d.comb += self.perm[i].eq(self.rb[index])
  File "/home/colepoirier/src/nmigen/nmigen/hdl/ast.py", line 253, in
__getitem__
    raise TypeError("Cannot index value with {}".format(repr(key)))
TypeError: Cannot index value with (slice (sig rs) 0:8)

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