[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Fri May 15 23:14:10 BST 2020
https://bugs.libre-soc.org/show_bug.cgi?id=316
Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:
What |Removed |Added
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CC| |lkcl at lkcl.net
--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #1)
> The code below is what I have so far in my first attempt at solving this
> problem:
good for you! throw it into... mmm... let's see...
soc/src/soc/logical/bperm.py
something like that.
> from nmigen import Elaboratable, Signal, Module, Repl, Cat
> from nmigen.cli import main
>
> class Bpermd(Elaboratable):
> def __init__(self, width):
> self.perm = Signal(width)
> self.rs = Signal(width)
> self.ra = Signal(width)
> self.rb = Signal(width)
>
> def elaborate(self, platform):
> m = Module()
> m.d.comb += self.perm.eq(Cat(0, Repl(8)))
> index = Signal(8)
> for i in range(0, 7 + 1):
> index = rs[8 * i:8 * i + 7 + 1]
> with m.If(index.lt(64)):
> m.d.comb += self.perm[i].eq(rb[index])
> with m.Else():
> m.d.comb += self.perm[i].eq(0)
> m.d.comb += ra.eq(Cat(Cat(0, Repl(56)),prem[0:8]))
> return m
>
> if __name__ == "__main__":
> bperm = Bpermd(width=8)
> main(bperm, ports=[bperm.perm, bperm.rs, bperm.ra, bperm.rb])
> ```
> m.d.comb += self.perm.eq(Cat(0, Repl(8)))
ok this needed to be:
m.d.comb += self.perm.eq(Repl(Const(0, 1), 8)))
or better just:
m.d.comb += self.perm.eq(Const(0, 8))
but to be honest you do not need to set it at all. if not set, the default
will be zero.
> TypeError: __init__() missing 1 required positional argument: 'count'
> ```
>
> I don't understand why I am getting the error that I'm missing a positional
> argument count in my __init__() function, since it only takes the parameters
> self and width.
Repl takes 2 arguments: the thing to replicate, and the number of times to
replicate it.
you passed only one argument.
> I'm sure this error is just due to my not understanding
> nmigen properly yet, so any help will be very much appreciated.
change this
with m.If(index.lt(64)):
to this
with m.If(index < 64):
and this
m.d.comb += ra.eq(Cat(Cat(0, Repl(56)),prem[0:8]))
to just this:
m.d.comb += ra[0:8].eq(perm)
because you want the answer in the 1st 8 bits, and perm you know is 8 bits.
actually you could just do ra.eq(perm) but nmigen might try to bit-extend
perm out to 64 bits, and that's a waste, because, again, if not set, the
bits will default to being set to zero.
he said.
they better be :)
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