[libre-riscv-dev] daily kan-ban update 22may2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri May 22 16:02:25 BST 2020

little late.  yesterday and this morning

* helped Michael go over the Condition Register pipeline reorg.  the CR
regfile is to be split into 8 4bit registers rather than one massive 32 bit
* sorted new CR register allocation scheme for when we put a CompUnit in
front of it
* described to Cesar the design mod requirements to ALUCompUnit needed: to
add selection of RA being a zero immediate and to bypass RD.REQ[0] when
that happens.
* added a zero_a flag to Decode2ExecuteType to support that
* reorganised the soc.fu code a little after separating out the op subsets
CompBrOpSubset etc
* cookie cut shiftreg and logical to soc.fu.mul and soc.fu.div
respectively, and placed some stub code for replacing with ieee754fpu
pipeline stages, for Jacob
* helped Jean-Paul in understanding the FU-FU Dependency Matrix so he can
do a layout experiment in coriolis2
* attended both OpenPOWER weekly coffee calls which were nice to do,
especially learning about microwatt first boot and also what Cesar does.
both very cool.

y'know... i have to say, i am not often aware at the time because i take
breaks and binge watch series episodes (Stargate SG1 at present, but only
because i ran out of American Ninja Warrior episodes), but each day when
actually written out does seem to be one hell of a lot.  this probably
because i don't do anything else, the entire day.



* draw out a new ALUCompUnit diagram for documentation purposes
* keep an eye out for Cole.  i couldn't work it out, either.  might need
your help, Michael.
* keep thinking through the multi comp unit data structures.
* answer issues as they come up


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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