[libre-riscv-dev] daily kan-ban update 08mar2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri May 8 16:25:55 BST 2020
On Fri, May 8, 2020 at 3:03 PM Michael N <mtnolan2640 at gmail.com> wrote:
> > On May 8, 2020, at 9:28 AM, Michael Nolan <mtnolan2640 at gmail.com> wrote:
> > Now that I have branches working in the simulator, I was thinking of starting work on the integer ALU. Taking a look at alu_hier.py, I think I'll keep the interface but replace the implementation with a pipelined one.
> > --Michael
> I noticed alu_hier was nicely broken up into different function units (adder, branch unit, multiplier, etc.).
yes, with an "op" - which in our case will basically be "decoder.InternalOp"
> Is there a nice way you know of to do that with the nmutil pipeline stages?
yyyess.... except it's too complicated to explain right just this
minute. raise the question in the bugreport.
> Like a way to merge stage 1 of the adder pipe with stage one of the branch pipe to get the stage 1 of the alu?
ok if you are talking about *outside* of ReservationStations, you are
mixing "purposes". the Branch pipeline *does not* interact - at all -
with the ALU pipeline.
can you look again at Mitch's ScoreBoard Mechanics1.pdf
damnit this needs to be on the bugreport, i haven't got time, 10m until meeting
see page 8, diagram at the top.
Those 4 batches of Function Units are *completely separate*. they do
basically, the first ALU, do it entirely as combinatorial just as in
alu_hier.py and assume only one clock cycle. leave out MUL and DIV
because those i believe need to be minimum 2 stages for MUL and a
*lot* for DIV.
actually you know what, screw it: make separate ones for MUL and DIV,
pretty much exactly like in that diagram on p8. we're doing a
radically different design as a proof-of-concept.
* add sub neg compare logical shift all go in their own
* MUL in its own separate RS/FU
* DIV likewise
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