[libre-riscv-dev] daily kan-ban update 25may2020

Cole Poirier colepoirier at gmail.com
Tue May 26 01:11:25 BST 2020

On May 25 2020, at 4:40 pm, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> On Tuesday, May 26, 2020, Cole Poirier <colepoirier at gmail.com> wrote:
>> https://opencores.org/websvn/filedetails?repname=wb_lpc&
>> path=%2Fwb_lpc%2Ftrunk%2Frtl%2Fverilog%2Fserirq_host.v
>> Once you let me know if this is correct I'll add it to the wiki and
>> crossref with bug 304.
> it looks like it.  we can ask Raptor Engineering.

Ok. I'll make a note on bug 304 that you will ask Raptor engineering
about this document? Then after we have confirmed I'll add it to the
repo in our mdwn file format for referencing external resources, and
note on this on the bug report.

> yes.  the multiport Regfile one.
> https://bugs.libre-soc.org/show_bug.cgi?id=351
> it should be simple to do, it is just to use Cat() on the 8 ports data.
> however it should be done under a Mux which ensures only one reader/writer
> i will write more in the bugreport.
> this one is time sensitive.

Awesome! I'll start now.

>> Possibly some formal proofs that I could see if I can crack?
> actually one for Regfile and RegfileArray would be good.
> if you can raise a bugreport about that?

Will do this now then start on the multiport regfile task.


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