[libre-riscv-dev] [Bug 351] New: create a "block" (mass) regfile port (read and write) onto an array-based regfile

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=351

            Bug ID: 351
           Summary: create a "block" (mass) regfile port (read and write)
                    onto an array-based regfile
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

see soc.regfile.RegFileArray

for the Condition Regfile and for the XER Regfile, a "mass-hit" read/write
port is required that looks like a standard read_port (or write_port) however
permits writing to the *entire* regfile, all at once.

this can be done as a virtual port, as follows:

* create 8x read (or write) ports
* join all 8 data together as if they were a single thing
* join all 8 "enable" lines together as if they were a single thing

it will however be critical to ensure that the alternative "view" is not
used at the same time.

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