[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue May 26 00:55:07 BST 2020


--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok so first derive from RegFileArray.

use the two parameters as follows:

* bitwidth: the TOTAL number of bits
* n_regs: the number of subdivisions of those bits.

therefore RegfileArray n_regs = nregs

however RegfileArray regwidth is bitwidth DIVIDED by n_regs.

then, in the constructor, add n_regs read ports and n_regs write ports to a
pair of lists.

you can see this being done in soc.regfile.regfiles here


except, that should be a for loop

next, we want an EXTRA read port and an extra write port.

this should, for data, instead of being only bitwidth/nregs wide, should
instead be the FULL bitwidth wide. 

however the enable lines should be nregs wide.

39         port = RecordObject([("ren", nregs),
  40                              ("data_o", bitwidth)],
  41                             name=name)

like that.

then, in the elaborate:

* if any of the "extra" port ren bits are set, the data is sent through the
corresponding *lower* indexed ports.

you see how that works?

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