[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=351

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=HEAD

saw this.


i think... actually... the list  of ports in the constructor, have to be done
manually, then those wired via a mux to the "real" ports

so a for loop adds RecordObjects

ren=1, data=bitwidth/nregs

then appends an *extra* on
ren=nregs, data=bitwidth


then in the constructor:

* test port[-1].ren == 0

* if zero then for all ports 0 to nregs, connect *internal* port to external
port

* else put bitwidth/nregs bits of port[-1].data onto port[loopindex].data and
also do same with enable bits.

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