[libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=319

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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           Assignee|lkcl at lkcl.net               |mtnolan2640 at gmail.com

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
michael could you convert all the outgoing XER fields to a Data record type?
this basically treating them just like spr1 2 3 which are Data type

what can then be done is, in the main_stage.py set the "ok" flag of carry32.ok
to 1 to indicate a *desire* to have the output_stage compute cr32 and so on.

each mainstage can then set those ok bits as needed.

some of those flags i think we might get already from the CSV files

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