[libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 20 05:10:19 BST 2020


--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ah.  right.  ok.  in alu/output_stage.py the Data ok for cr0 and the XER fields
do, ov, ov32, need to be set based on  Rc and OE from the instruction.

CR0                     (if Rc=1)
SO OV OV32             (if OE=1)

this code shows that the op.carry_out field from op decode is Rc

and that op.oe is likewise OE.

carry_32 := result(32) xor a_inv(32) xor b_in(32);
carry_64 := result_with_carry(64);
if e_in.insn_type = OP_ADD then
    if e_in.output_carry = '1' then
       set_carry(v.e, carry_32, carry_64);
    end if;
    if e_in.oe = '1' then
               calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
               calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
    end if;

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list