[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri May 15 19:58:23 BST 2020


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hmm hmm i thought perhaps instead of passing nia into all ALUs (where it would
then not actually be used - the wires would be routed, taking up space but
then not actually go anywhere), to create a separate CompBROpSubset?

then, likewise in CompBROpSubset, anything _not_ used in any branch operation
can be removed from it.

diff --git a/src/soc/alu/alu_input_record.py b/src/soc/alu/alu_input_record.py
index 2c3dcc4..41a40eb 100644
--- a/src/soc/alu/alu_input_record.py
+++ b/src/soc/alu/alu_input_record.py
@@ -13,7 +13,6 @@ class CompALUOpSubset(Record):
     def __init__(self, name=None):
         layout = (('insn_type', InternalOp),
                   ('fn_unit', Function),
-                  ('nia', 64),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                     #'cr = Signal(32, reset_less=True) # NO: this is from the
                     #'xerc = XerBits() # NO: this is from the XER SPR

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list