[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
interesting!

    # XXX - immediate and zero is not a POWER mode (and won't work anyway)
    # reason: no actual operands.
    #result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
    #                                imm=8, imm_ok=1)
    #assert result == 8

this test is invalid, because it effectively is a "update register with
immediate", disabling both A and B regs.

i believe there are other opcodes to cover this, therefore it is not a
valid test.   which is good because the FSM doesn't cope with it
(it relies on at least one RD.GO coming in, and if both operands are
immediates, that can never happen)

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