[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
argh yes it is a valid test.  there is an add zero immediate instruction.

so this means rd_done will never be set, and the FSM never proceeds to
completion on 2-operand CompUnits

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