[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #19)

> When I did the above, I noticed src/soc/experiment/compalu.py and
> src/soc/experiment/compldst.py have been suffering from bitrot. I suppose
> they are previous attempts, no longer updated, and kept for historical
> reasons?

they're only there from the transition to multi-bit RD/WR signalling.

-- 
You are receiving this mail because:
You are on the CC list for the bug.