[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #19 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #18)
> (In reply to Luke Kenneth Casson Leighton from comment #17)
> 
> > btw, commit this immediately - do not wait to "accumulate" a series of
> > commits,
> 
> nicely done, cesar.
> 
> commit a5968ecf27c0be3b357342889aaa8e48c1a519cb
> Author: Cesar Strauss <cestrauss at gmail.com>
> Date:   Sun May 24 16:44:12 2020 -0300
> 
>     Rename the internal DFF of latchregisters to avoid conflict

Thanks.

When I did the above, I noticed src/soc/experiment/compalu.py and
src/soc/experiment/compldst.py have been suffering from bitrot. I suppose they
are previous attempts, no longer updated, and kept for historical reasons?

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