[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 20 20:46:21 BST 2020


https://bugs.libre-soc.org/show_bug.cgi?id=333

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #7)

> So for this module, how would that work? I'm assuming we wouldn't be passing
> in all 8 CRs, because that would be just as bad as what we have now. But we
> need the full CR for mfcr and mtcrf. Would we have 2 small cr inputs as well
> as the full cr, and depending on whether which opcode it is we select which
> one to use?

yes basically.  perhaps even use the 32 bit path to get the smaller regs to it.

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