[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=333

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
just as spr and reg is decoded in power_decode2.py for RA RB RC and output, csv
files would have "reg is CR" enum option.

each DecodeRegA (etc) would then note that and place BFA insn fields (etc) into
not a reg_data or an spr_data but a cr_data field and indicate that they are
valid.

these - 3 - CR reg fields then get put into Execute1Type just like reg and spr
data.

CrOpSubset (to be created) then picks those up.

the instruction issue would also note them and request DM Matrix Reservations
just like it would for RA RB RC RS/T except for the Condition Regfile (and
Matrix) not the INT regfile.

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