[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=333

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hm need to decide the register allocation scheme.  it is ok to have 4bit CR go
into a 32bit operand but not to have CR data go down an INT path.

or, if we do, MUXes are needed to cross data from one series of regfile paths
to another.

this could be done for when we have the cyclic buffers in place, easily.

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