[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #5 from Jacob Lifshay <programmerjake at gmail.com> ---
I wrote a simple Rust program that runs different Power instructions (just div*
and mod* for now) and put the results here:
https://salsa.debian.org/Kazan-team/power-instruction-analyzer/-/blob/master/output-for-initial-2-ga7250d2.txt

Source here:
https://salsa.debian.org/Kazan-team/power-instruction-analyzer

result_prev is assigned to the result register before executing the tested
instruction since sometimes processors just skip writing to a register in
exceptional cases

>From what I can tell, for all error cases for div and mod instructions, POWER9
just writes 0 to the result register.

For the instructions with just 32-bit results, from what I can tell from a
relatively small number of test cases, it zero extends for all signed/unsigned
div instructions, zero extends for unsigned mod instructions, and sign extends
for signed mod instructions.

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