[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #46 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #43)
> (In reply to Michael Nolan from comment #42)
> 
> > I went through the tables and double checked, the *only* ALU instructions
> > that have 3 inputs are 2 registers and an immediate. It does not *need* 3
> > register inputs. 
> 
> yehyeh.  ok.
> 
> really... normally, what would happen is that anything that's significantly
> different like this would get put into its own Function Unit (into its own
> ALU Pipeline).

https://libre-soc.org/openpower/isa/fixedshift/

... actually... you know what?  all of those are M-Form and MD-Form

whereas, quickly analysing these:
https://libre-soc.org/openpower/isa/fixedarith/

they're D-Form, DX-Form, XO-Form, and XO-Form.

some of the weird ones (addex) are Z23-Form, and the MAC ones are VA-Form

on balance therefore it kinda makes sense to split fixedshift out into
its own separate ALU / pipeline.  aside from anything, it may turn out
to be the case that whilst add, sub etc. can be done in a single clock,
shift has a strong possibility of needing 2 (in really high speed
designs).  that would be easier to do if they were separate pipelines.

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