[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=216

--- Comment #30 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://www.youtube.com/watch?v=6Yiyw4abJpE

a walkthrough video which explains the components (the ones that
already exist) and explains what's needed.  crucially, the existing
components provide certain guarantees that, by the time it comes
to what the L0 Cache/Buffer has to do, is a ridiculously simple
job.

i forgot to mention: after the PriorityPicker, the "selection" of the
units which are "above" that first-picked row, we actually already
have some code which does that: michael wrote it, for the LE/GE/EQ
"PartitionedSignal" comparators.

the class is called "RippleLSB":
https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part_cmp/ripple.py;h=032512047f2e58c3ce50bc869e4a064738647943;hb=cec6f51e8b2a1ba2c2f83965be7219885ea163f0#l13

this can be moved to nmutil.

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