[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu May 21 19:34:36 BST 2020


--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #16)
> (In reply to Michael Nolan from comment #15)
> > Ok. I notice there's now a regspec array for the input and output data
> > structs. What would a 4 bit CR be?
> ermmm... ermermerm.... probably just "CR", and a range "0:3" (it's inclusive,
> unlike python slices)

ok sorry:

* for the field that's supposed to fit the full CR, it remains 0:31 (32 bits)

  we will drop only 4 bits into it for src-cr-A (read_cr1) for BA,
  and a full 32-bits for CR_MTCRF (etc) involving XFX mask.

  so src-cr-A would need to be a full 32-bit wide.

* for the 2nd field, it will be 0:3 (4 bits)

  there it will only be 4 bits wide so src-cr-B operand would only be 4 bits

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