[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=333

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #15)

> Ok. I notice there's now a regspec array for the input and output data
> structs. What would a 4 bit CR be?

ermmm... ermermerm.... probably just "CR", and a range "0:3" (it's inclusive,
unlike python slices)

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