[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=333

--- Comment #15 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)
> (In reply to Luke Kenneth Casson Leighton from comment #12)
> 
> > however the (planned) cyclic buffers now become even more complex, because
> > each register could contain two values not one.
> 
> answer: it would not be a good idea. much simpler - cleaner - to have extra
> 4 bit data path(s) for the src CR regs that won't go into src1.
> 
> remember, it would mean that *at the regfile* access to a *pair* of 4 bit
> Read Ports would need to be synchronised, just to make the transfer of 2
> simultaneous 4 bit values down that one 32 bit path.
> 
> this in addition to making the cyclic buffers far more complex.

Ok. I notice there's now a regspec array for the input and output data structs.
What would a 4 bit CR be?

-- 
You are receiving this mail because:
You are on the CC list for the bug.