[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #25)
> (In reply to Luke Kenneth Casson Leighton from comment #24)
> > https://github.com/antonblanchard/microwatt/blob/master/ppc_fx_insns.vhdl
> > 
> > line 563 is where sraw, srad, srawi and sradi exist.  there's a *lot*
> > of code-duplication, which is fairly normal in "traditional" HDLs because
> > parameterisation can be harder to do.
> 
> Those are already done in main_stage.py,

nice.

> though they could do with a bit
> more rigorous testing.

i noticed an assert on bits in SelectableInt not being happy.

cmp by the way apologies for moving the add into the switch statement.

don't do trap in this Function Unit, it changes the PC so i think really should
be in a special FunctionUnit which outputs a new PC, alongside Branch etc.

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