[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #13)

> Still need a way to test the case of zero_a and/or imm_data being entirely
> absent, in which case the muxes are not generated.

ah if you create a test which uses... mmm.... which one is dead-simple...
CompCROpSubset, then that doesn't have imm_data or zero_a.

see soc.experiment.alu_hier.DummyALU

i've just added a DummyALU for you, it ignores operand b, ignores the
actual operand type (up to you if you want to put that back, do something
different), just copies a to o - nothing sophisticated.

so you can copy test_compunit_regspec1(), call it test_compunit_regspec2()
then cookie-cut scoreboard_sim() and op_sim() to remove trying to set imm_data,
invert_a, and zero_a (because those don't exist in CompCROpSubset), and
just assert that the result is equal to the 1st operand, a.

if you really wanted to you could actually remove b from the inspec in
test_compunit_regspec2() and also in DummyALU.

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