[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #13 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)
> brilliant, just saw this, Cesar.  confirmed that it is functional.
> 
> commit 260625df9309f8f35541207cab431dd8dba90c5a
> Author: Cesar Strauss <cestrauss at gmail.com>
> Date:   Sat May 23 19:52:08 2020 -0300
> 
>     Add a few test cases with zero_a set, in combination with imm_ok
> 

Still need a way to test the case of zero_a and/or imm_data being entirely
absent, in which case the muxes are not generated.

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