[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu May 21 19:56:03 BST 2020


--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
class CROutSel(Enum):
    NONE = 0
    CR0 = 1
    BF = 2
    BT = 3
    WHOLE_REG = 4

ah.  whoops.  minor_31.csv, CR0 has been put as the "CR in", where it should be
"NONE", and it should be "CR out" that should be CR0.

i will adjust minor_31.csv

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