[libre-riscv-dev] Debug port (was Re: minimum viable ASIC)

[Luke Kenneth Casson Leighton]

On Wednesday, May 20, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

import nmigen as nm
> x = nm.Signal()
>
> is actually a really good idea.  saves space, explicitly says where
> the "thing" (Signal etc.) come from.


i found some code where we do just module import:

https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/singlepipe.py;h=cbd06f648b23a3ad6e9b064093de0f039c76bb32;hb=HEAD#l877

similar to "import operator" or "import math" then use

math.pi
math.cos(x)
operator.add

etc.

this is very good practice, Staf, because it allows the reader, at the
point of use of the function or class, to know immediately without
scrolling to the top of the page, which module the code comes from.

whilst *you* might know that, other readers will not.  the additional
context is critical for *their* understanding and to not force them to work
harder, slowing them down to the point where mistakes are made or they give
up and find someone else's code.

bottom line: it's not about you :) these are practices that make life
easier for *other people*.

l.




-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68