[libre-riscv-dev] Rough timing estimate in yosys
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon May 18 16:05:00 BST 2020
On Monday, May 18, 2020, Michael Nolan <mtnolan2640 at gmail.com> wrote:
> With all the work going on designing functional units, I was wondering if
> there was a way to get a rough estimate of the maximum frequency a module
> can run at. I can get the longest path from running yosys -p "read_ilang
> module.il; synth; ltp", but that just prints out the cells between
> register A and register B.
oh, good. that's a useful discovery.
> I realize that the actual timing is going to depend on layout, but is
> there a way to get a rough estimate, say by passing in a cell library or
> just a rule of thumb of ~500ps per cell?
i believe it is calculated based on the switching time of a given
transistor, at both the geometry, and also a given voltage.
a chain of such transistors is then multiplied by the longest path.
at the speeds we are doing, speed of light is not a major factor: it will
be however at 28nm or below.
also affecting the switching time is the fanout. if one gate tries to
drive 200 clearly this will either fail or just take a hell of a long time.
to solve that, buffers must be inserted into the line and of course those
also add switching delay.
> On a semi-related note, running ltp on a pipeline shows that there's a
> bunch of loops.
> From running synth and ltp on the logical pipeline:
> Warning: Detected loop at \stage_o$next  in pipe
hmm i do not know.
we are doing an design where the registers can be held until acknowledged
by ready/valid signalling: it's possible that the storage of the register
is interpreted as "a loop".
can you raise a bugreport about it so thatbit can be investigated? mention
that a small unit test should be made.
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