[libre-riscv-dev] Rough timing estimate in yosys

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon May 18 16:52:29 BST 2020

On Monday, May 18, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

>> Warning: Detected loop at \stage_o$next [63] in pipe
> we are doing an design where the registers can be held until acknowledged
> by ready/valid signalling: it's possible that the storage of the register
> is interpreted as "a loop".
> can you raise a bugreport about it so thatbit can be investigated?
> mention that a small unit test should be made.


ok yes that's fine.

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