[libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri May 8 17:55:52 BST 2020
On Fri, May 8, 2020 at 4:27 PM <whygee at f-cpu.org> wrote:
> To me JTAG/TAP/debug port shine from its absence.
yep good catch. added.
l.
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