[libre-riscv-dev] Debug port (was Re: minimum viable ASIC)

whygee at f-cpu.org whygee at f-cpu.org
Fri May 8 16:27:06 BST 2020

On 2020-05-08 11:50, Luke Kenneth Casson Leighton wrote:
> i'd like to discuss what the minimum viable ASIC would look like,
> that, if we're happy to do so, we could hit the October 2020 deadline
> with it and not be completely stressed.
> thoughts appreciated.

To me JTAG/TAP/debug port shine from its absence.

how will you "talk" with the chip when it
arrives from factory and you want to ensure
all its pins are correctly soldered/bonded
and you want to explore the insides to
test each unit ?

> l.

More information about the libre-riscv-dev mailing list