[libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
staf at fibraservi.eu
Fri May 8 18:23:35 BST 2020
Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 17:55 [+0100]:
> On Fri, May 8, 2020 at 4:27 PM <whygee at f-cpu.org> wrote:
> > To me JTAG/TAP/debug port shine from its absence.
> yep good catch. added.
I already have (alpha version) nmigen JTAG code: https://gitlab.com/Chips4Makers/c4m-jtagStaf. id="-x-evo-selection-start-marker">
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