[libre-riscv-dev] Debug port (was Re: minimum viable ASIC)

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Fri, May 8, 2020 at 6:23 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
>
> Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 17:55 [+0100]:
> > On Fri, May 8, 2020 at 4:27 PM <whygee at f-cpu.org> wrote:
> > > To me JTAG/TAP/debug port shine from its absence.
> >
> > yep good catch.  added.
>
> I already have (alpha version) nmigen JTAG code: https://gitlab.com/Chips4Makers/c4m-jtag
> Staf. id="-x-evo-selection-start-marker">

found the link (minus HTML error)
https://gitlab.com/Chips4Makers/c4m-jtag

ah.  as a software engineer, the practice of using wildcard imports is
an extremely bad one.  i strongly advocate *not* getting into the
habit of doing "from nmigen import *" everywhere - it will make your
life - and other users lives - absolute hell when it comes to trying
to track and debug code.

minerva has a JTAG interface as well.  i corrected the practice of
using "import *" in this one

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/units/debug/controller.py;h=7304303e577b14eebba15144642eb7bee829e107;hb=a54adcb65bad37b398b11e33a824c7d08c5fe509

it looks like the minerva team got a long way with that.  also
provided a wishbone master interface:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/units/debug/wbmaster.py;h=db02af95b4eb3ef8ac25b348f3abaa2bcbe7d96f;hb=a54adcb65bad37b398b11e33a824c7d08c5fe509

l.