[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
* did the usual code-morphs blah blah just to make me feel happy
  (and also so i know what the code is doing, so i feel confident
  when it comes to connecting it up).

  i'm done with that :)

* branch's data structure uses Data to indicate when things
  are updated.  i felt it might be sensible to keep a consistent
  API so did the same thing to Trap's data structure.

  thus, o.nia.ok, o.srr0.ok and o.srr1.ok are all set to 1
  when the trap signals "go"

  these signals, for the two SPRs, can be wired directly to
  the FunctionUnit "WRITE_REQUEST" signals with no additional
  logic needed for decoding the operand at the FunctionUnit.

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