[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> (In reply to Jacob Lifshay from comment #4)
> > I think this should also cover interrupts.
> > 
> > I would suggest having the execution unit be a FSM since traps/interrupts
> > are rare, so the FSM is not activated unless a trap/interrupt is taken. When
> > we receive an external interrupt, we could switch the decoder to insert a
> > special trap instruction instead of decoding normally.
> 
> traps are stunningly simple, the only thing they do is change the MSR and
> NIA (program counter).  and change SRR0 and SRR1. it is hardly even an FSM :)
> 
> i like the interrupt idea, i believe it is kinda expected to do this.

hints of this technique:

irq_valid := '0';
if ctrl.msr(MSR_EE) = '1' then
    if ctrl.dec(63) = '1' then
        ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
        report "IRQ valid: DEC";
        irq_valid := '1';
    elsif i_in.irq = '1' then
        ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#500#, 64));
        report "IRQ valid: External";
        irq_valid := '1';
    end if;
end if;

so hypothetically, yes, we could create an OP_IRQ that is covered by this
pipeline and is responsible for changing nia etc.

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