[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
here is the continuation of that process (the FSM in microwatt which has to
take a couple of cycles to write out SRR0/1)

the first bit drops SRR1 into the SPR regfile (we can do 1 cycle) then moves on

the second elsif is near identical to TRAP except it sets the priv bit in the
outgoing MSR.

this we would need to detect at the instruction issue phase (MSR PR bit set)
and yes that is a pain in the neck, for *issue* phase to have to do that.

however once detected, again, an internal OP_INTPRIVthing can be created, sent
to the Trap pipeline for it to action and generate SRR1 and 0


elsif irq_valid = '1' and e_in.valid = '1' then
    -- we need two cycles to write srr0 and 1
    -- will need more when we have to write HEIR
    -- Don't deliver the interrupt until we have a valid instruction
    -- coming in, so we have a valid NIA to put in SRR0.
    exception := '1';
    ctrl_tmp.srr1 <= msr_copy(ctrl.msr);

elsif e_in.valid = '1' and ctrl.msr(MSR_PR) = '1' and
            instr_is_privileged(e_in.insn_type, e_in.insn) then
    -- generate a program interrupt
    exception := '1';
    ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
    ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
    -- set bit 45 to indicate privileged instruction type interrupt
    ctrl_tmp.srr1(63 - 45) <= '1';
    report "privileged instruction";

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