[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
suggest adding mfmsr and mtmsr to TRAP pipeline.  does mean adding RT and MSR
as additional output regs.

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