[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue May 19 19:13:27 BST 2020


--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)
> I think this should also cover interrupts.
> I would suggest having the execution unit be a FSM since traps/interrupts
> are rare, so the FSM is not activated unless a trap/interrupt is taken. When
> we receive an external interrupt, we could switch the decoder to insert a
> special trap instruction instead of decoding normally.

traps are stunningly simple, the only thing they do is change the MSR and NIA
(program counter).  and change SRR0 and SRR1. it is hardly even an FSM :)

i like the interrupt idea, i believe it is kinda expected to do this.


You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list