[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=313

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
waaaa...

    insn       CR  SPR1  SPR2    SPR3
    ----       --  ----  ----    ----
    op_b       xx  LR     xx     xx
    op_ba      xx  LR     xx     xx
    op_bl      xx  LR     xx     xx
    op_bla     xx  LR     xx     xx
    op_bc      CR, LR,    CTR    xx
    op_bca     CR, LR,    CTR    xx
    op_bcl     CR, LR,    CTR    xx
    op_bcla    CR, LR,    CTR    xx
    op_bclr    CR, LR,    CTR    xx
    op_bclrl   CR, LR,    CTR    xx
    op_bcctr   CR, LR,    CTR    xx
    op_bcctrl  CR, LR,    CTR    xx
    op_bctar   CR, LR,    CTR,   TAR
    op_bctarl  CR, LR,    CTR,   TAR

    op_sc      xx  xx     xx     MSR
    op_scv     xx  LR,    SRR1,  MSR
    op_rfscv   xx  LR,    CTR,   MSR
    op_rfid    xx  SRR0,  SRR1,  MSR
    op_hrfid   xx  HSRR0, HSRR1, MSR

and if we did TRAP in the Branch pipeline as well, that would be
*six* incoming 64-bit register latch paths.  nooo, i don't think so :)

so the above table should guide the numbering.  LR - that's not an SPR,
is it?  if not, then ho hum we should call the field lr_or_spr1 or something
horrible.  not a huge fan of long data structure names, but hey :)

* the BranchCompUnit should expect to read the SPR regfile and allocate
  lr_or_spr1, spr2, and spr3 accordingly.
* BranchInputData should be the target recipient of that data
* branch/main_stage should decode the three fields lr_or_spr1, spr2 and spr3
  likewise according to that table.

for op_bc* that's dead simple: lr = lr_or_spr1, ctr = spr2, tar = spr3

for op_sc and other system calls it's more complex, but doable.

-- 
You are receiving this mail because:
You are on the CC list for the bug.