[libre-riscv-dev] Power ISA v3.1 bug - parityw
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed May 27 23:09:31 BST 2020
On Wednesday, May 27, 2020, Paul Mackerras <paulus at ozlabs.org> wrote:
> > The description of "least significant bit in each byte" leads me to
> > that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it is
> > implemented in microwatt
> The IBM Power architects have confirmed that it should be
> multiplication rather than remainder, i.e. RS[i*8+7] as you suggest.
super. i can see from the revisions (3.0B -> 3.1B) that it was copied from
a divmod algorithm.
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