[libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw

[Paul Mackerras]

On Fri, May 15, 2020 at 11:07:12AM -0400, Michael Nolan wrote:
> Hello! I'm with the Libre-SOC team, and was working on testing our
> implementation of the parityw and parityd instructions when I came across
> the following bug in the specification. The specification describes prtyd as
> follows:
> 
> s <- 0
> 
> do i = 0 to 7
> 
>     s <- s (XOR) RS[i%8 + 7]
> 
> RA <- 63'b0 || s
> 
> The least significant bit in each byte of the contents of register RS is
> examined. If there is an odd number of one bits the value 1 is placed into
> register RA; otherwise the value 0 is placed into register RA.
> 
> 
> 
> The description of "least significant bit in each byte" leads me to believe
> that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it is
> implemented in microwatt

The IBM Power architects have confirmed that it should be
multiplication rather than remainder, i.e. RS[i*8+7] as you suggest.

Paul.