[libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw
paulus at ozlabs.org
Tue May 26 06:44:30 BST 2020
On Fri, May 15, 2020 at 11:07:12AM -0400, Michael Nolan wrote:
> Hello! I'm with the Libre-SOC team, and was working on testing our
> implementation of the parityw and parityd instructions when I came across
> the following bug in the specification. The specification describes prtyd as
> s <- 0
> do i = 0 to 7
> s <- s (XOR) RS[i%8 + 7]
> RA <- 63'b0 || s
> The least significant bit in each byte of the contents of register RS is
> examined. If there is an odd number of one bits the value 1 is placed into
> register RA; otherwise the value 0 is placed into register RA.
> The description of "least significant bit in each byte" leads me to believe
> that RS[i%8 + 7] should really be RS[i*8+7]. This is also how it is
> implemented in microwatt
Right, and microwatt matches POWER9, so POWER9 implements "*" as well.
I have asked the IBM architects for confirmation, and I'll let you
know what they say. For now I think it's pretty safe to go ahead with
"*", since "*" is clearly what existing software expects.
More information about the libre-riscv-dev