[libre-riscv-dev] Power ISA v3.1 bug - parityw

[Luke Kenneth Casson Leighton]

On Fri, May 15, 2020 at 4:07 PM Michael Nolan <mtnolan2640 at gmail.com> wrote:

> s <- 0
>
> do i = 0 to 7
>
>      s <- s (XOR) RS[i%8 + 7]

we note that in V3.0B this was s <- s / RS[I%8 + 7] - divide and
modulo rather than XOR and multiply.

l.